pack4xAlphaValues
This commit is contained in:
parent
f9813d054c
commit
7195d0a74d
2 changed files with 12 additions and 25 deletions
|
@ -542,26 +542,15 @@ proc newMask*(image: Image): Mask {.raises: [PixieError].} =
|
||||||
var i: int
|
var i: int
|
||||||
when defined(amd64) and not defined(pixieNoSimd):
|
when defined(amd64) and not defined(pixieNoSimd):
|
||||||
for _ in 0 ..< image.data.len div 16:
|
for _ in 0 ..< image.data.len div 16:
|
||||||
var
|
let
|
||||||
a = mm_loadu_si128(image.data[i + 0].addr)
|
a = mm_loadu_si128(image.data[i + 0].addr)
|
||||||
b = mm_loadu_si128(image.data[i + 4].addr)
|
b = mm_loadu_si128(image.data[i + 4].addr)
|
||||||
c = mm_loadu_si128(image.data[i + 8].addr)
|
c = mm_loadu_si128(image.data[i + 8].addr)
|
||||||
d = mm_loadu_si128(image.data[i + 12].addr)
|
d = mm_loadu_si128(image.data[i + 12].addr)
|
||||||
|
|
||||||
a = packAlphaValues(a)
|
|
||||||
b = packAlphaValues(b)
|
|
||||||
c = packAlphaValues(c)
|
|
||||||
d = packAlphaValues(d)
|
|
||||||
|
|
||||||
b = mm_slli_si128(b, 4)
|
|
||||||
c = mm_slli_si128(c, 8)
|
|
||||||
d = mm_slli_si128(d, 12)
|
|
||||||
|
|
||||||
mm_storeu_si128(
|
mm_storeu_si128(
|
||||||
result.data[i].addr,
|
result.data[i].addr,
|
||||||
mm_or_si128(mm_or_si128(a, b), mm_or_si128(c, d))
|
pack4xAlphaValues(a, b, c, d)
|
||||||
)
|
)
|
||||||
|
|
||||||
i += 16
|
i += 16
|
||||||
|
|
||||||
for j in i ..< image.data.len:
|
for j in i ..< image.data.len:
|
||||||
|
@ -850,22 +839,12 @@ proc drawUber(
|
||||||
backdrop = mm_loadu_si128(a.data[a.dataIndex(x, y)].addr)
|
backdrop = mm_loadu_si128(a.data[a.dataIndex(x, y)].addr)
|
||||||
when type(b) is Image:
|
when type(b) is Image:
|
||||||
# Need to read 16 colors and pack their alpha values
|
# Need to read 16 colors and pack their alpha values
|
||||||
var
|
let
|
||||||
i = mm_loadu_si128(b.data[b.dataIndex(sx + 0, sy)].addr)
|
i = mm_loadu_si128(b.data[b.dataIndex(sx + 0, sy)].addr)
|
||||||
j = mm_loadu_si128(b.data[b.dataIndex(sx + 4, sy)].addr)
|
j = mm_loadu_si128(b.data[b.dataIndex(sx + 4, sy)].addr)
|
||||||
k = mm_loadu_si128(b.data[b.dataIndex(sx + 8, sy)].addr)
|
k = mm_loadu_si128(b.data[b.dataIndex(sx + 8, sy)].addr)
|
||||||
l = mm_loadu_si128(b.data[b.dataIndex(sx + 12, sy)].addr)
|
l = mm_loadu_si128(b.data[b.dataIndex(sx + 12, sy)].addr)
|
||||||
|
source = pack4xAlphaValues(i, j, k, l)
|
||||||
i = packAlphaValues(i)
|
|
||||||
j = packAlphaValues(j)
|
|
||||||
k = packAlphaValues(k)
|
|
||||||
l = packAlphaValues(l)
|
|
||||||
|
|
||||||
j = mm_slli_si128(j, 4)
|
|
||||||
k = mm_slli_si128(k, 8)
|
|
||||||
l = mm_slli_si128(l, 12)
|
|
||||||
|
|
||||||
let source = mm_or_si128(mm_or_si128(i, j), mm_or_si128(k, l))
|
|
||||||
else: # b is a Mask
|
else: # b is a Mask
|
||||||
let source = mm_loadu_si128(b.data[b.dataIndex(sx, sy)].addr)
|
let source = mm_loadu_si128(b.data[b.dataIndex(sx, sy)].addr)
|
||||||
|
|
||||||
|
|
|
@ -173,6 +173,14 @@ when defined(amd64) and not defined(pixieNoSimd):
|
||||||
result = mm_or_si128(mm_or_si128(result, i), mm_or_si128(j, k))
|
result = mm_or_si128(mm_or_si128(result, i), mm_or_si128(j, k))
|
||||||
result = mm_and_si128(result, first32)
|
result = mm_and_si128(result, first32)
|
||||||
|
|
||||||
|
proc pack4xAlphaValues*(i, j, k, l: M128i): M128i {.inline, raises: [].} =
|
||||||
|
let
|
||||||
|
i = packAlphaValues(i)
|
||||||
|
j = mm_slli_si128(packAlphaValues(j), 4)
|
||||||
|
k = mm_slli_si128(packAlphaValues(k), 8)
|
||||||
|
l = mm_slli_si128(packAlphaValues(l), 12)
|
||||||
|
mm_or_si128(mm_or_si128(i, j), mm_or_si128(k, l))
|
||||||
|
|
||||||
proc unpackAlphaValues*(v: M128i): M128i {.inline, raises: [].} =
|
proc unpackAlphaValues*(v: M128i): M128i {.inline, raises: [].} =
|
||||||
## Unpack the first 32 bits into 4 rgba(0, 0, 0, value)
|
## Unpack the first 32 bits into 4 rgba(0, 0, 0, value)
|
||||||
let
|
let
|
||||||
|
|
Loading…
Reference in a new issue